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RJ-017
ChipBridge
* Glueless connection to most * * * * * * * *
FEATURES
*
LAN chips Up to 40 Mbps Sync WAN link Up to 115.2 kbps Async WAN link with internal baud rate generator 10,000-address LAN table Buffer capacity of 256 frames Filtering rate of 15,000 pps Forwarding rate of 15,000 pps Automatic LAN table learning and aging Compression type: Enhanced Tinygram Full on-chip support for 7 status LEDs
* High performance, single chip, * * * * *
* Low power 0.6 micron CMOS
technology * 100-pin PQFP package
full remote Ethernet bridge, fully IEEE 802.3 compatible On chip AUI (DTE or DCE) or UTP LAN interfaces NRZ decoded signals for easy interface to other Ethernet chips 10 Mbps in half-duplex mode or 20 Mbps in full-duplex mode Automatic TP polarity reversal Multiple LAN operating modes
RJ-017
ChipBridge
DESCRIPTION
The ChipBridge is a highly integrated ASIC that combines LAN and WAN subsystems to achieve a full Ethernet remote bridge on a single chip. It automatically learns the MAC addresses on the LAN it is connected to, and forwards only the frames destined for another LAN. It is fully compliant with the IEEE 802.3 standard. The ChipBridge's LAN interface incorporates a Manchester encoder/decoder that allows AUI (DTE or DCE) and both half-duplex (10 Mbps) and full-duplex (20 Mbps) UTP operation modes. In addition, all LAN signals are available as NRZ decoded signals for connection to other LAN devices, such as multi-port repeaters or LAN controllers. In total, twenty-five different modes of operation can be selected by setting the LMODE input pins. The WAN subsystem contains a sync/async HDLC controller, capable of operating at up to 40 Mbps in synchronous mode, and 115.2 kbps in asynchronous mode. Zero-bit insertion and deletion is used in synchronous mode and octetstuffing is used in asynchronous mode for transparency. The ACCM (Async Control Character Map) can be disabled if not required (asynchronous mode only). In asynchronous mode, an external clock source may be used or the internal baud rate generator can be configured to generate standard clock frequencies between 9.6 kbps and 115.2 kbps. Enhanced Tinygram compression increases data throughput by stripping the padding bits in 64-byte frames.
The ChipBridge's LAN table can store up to 10,000 addresses and is automatically updated. The aging machine automatically deletes entries if, after 5 minutes, no frames have been received from that station. Filtering and forwarding is performed at the maximum theoretical rate of 15,000 pps. The ChipBridge buffer can hold 256 frames, with a throughput latency of 1 frame. Filtering can be disabled for those applications that require it, such as LAN extenders and segmenters. The ChipBridge operates independently without need for a host. The only external component required is a 256k x 16 DRAM, a crystal and some resistors and capacitors. The ChipBridge contains a DRAM controller for glueless connection to the DRAM. The ChipBridge is manufactured in low power 0.6 micron CMOS process and is available in a 100-pin PQFP package. The ChipBridge functional block diagram is seen in Figure 1 and the connection diagram in Figure 2.
2
RJ-017
ChipBridge
WTXD WTXC/WCLK WRXD WRXC/BAUD0 /WRTS /WCTS BAUD1 BAUD2 COMPR WMODE ACCM
TXD+ TXDTXP+/CO+ TXP-/CORXDTH+ RXDTHRXDIN RXDREF CITH+ CITHCIREF LMODE[4:0] LTXD LRTS LRXD LCRS LCDT LCTS
SYNC/ASYNC WAN CONTROLLER
/LNKINT /WANTX /WANRX /LANTX /LANRX /COLL /ERR
ETHERNET LAN CONTROLLER & ENDEC
LED
LP1 LP2 PLLVDD PLLVSS PLLAGND XOUT XIN CLKOUT CLK10M MD0-MD15
CLOCK GENERATOR
DRAM INTERFACE
MA0-MA8 /RAS /CAS /MWR
FLTDIS
FILTER
CONTROL
/RESET
Figure 1. Functional Block Diagram
3
RJ-017
ChipBridge
WRXC/BAUD0
WTXC/WCLK
CLKOUT
COMPR
/RESET
BAUD1
BAUD2
/WRTS
/WCTS
WTXD
WRXD
ACCM
100 99 VDD MD0 MD14 MD1 MD13 MD2 MD12 MD3 MD4 MD11 MD5 MD10 GND MD6 MD9 MD7 MD8 /MWR /RAS /CAS MA0 MA8 GND MA1 MA7 MA2 MA6 MA3 MA5 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MA4 32 GND
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 LP1 LP2 PLLAGND PLLVSS PLLVDD GND VDD WMODE VDD VDD LMODE4 LMODE3 LMODE2 LMODE1 LMODE0 TXD+ TXDTXP+/CO+ TXP-/CORXDTH+ RXDTHRXDIN RXDREF CITH+ CITHCIREF GND GND CLK10M VDD
XOUT 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 LCDT
MD15
GND
GND
GND 48 LCRS
VDD
VDD
100 PQFP TOP VIEW
33 /LNKINT
34 /WANTX
35 /WANRX
36 GND
37 //LANTX
38 /LANRX
39 /COLL
40 GND
41 /ERR
42 VDD
43 FLTDIS
44 LTXD
45 LRTS
46 GND
47 LRXD
49 LCTS
Figure 2. Connection Diagram
4
XIN
RJ-017
ChipBridge
PIN DESCRIPTION
Table 1. Pin Description Name
MA0-MA8
Pin No.
21, 22, 24, 25, 26, 27, 28, 29, 31 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 100 19
Type Description
O DRAM ADDRESS BUS: The DRAM address bus is multiplexed. During the first phase, it carries address bits 10-18, and during the second phase it carries address bits 1-9. DRAM DATA BUS: The DRAM data bus is an input while the ChipBridge is reading from the DRAM, and an output while writing to the DRAM. At all other times it is 3-state.
MD0 - MD15
I/O
/RAS
O
/CAS
20
O
/MWR WTXD
18 90
O O
WTXC/WCLK
89
I
WRXD
88
I
WRXC/BAUD0
87
I
/WRTS
97
O
DRAM ROW ADDRESS STROBE: This output drives the DRAM RAS signal. It is used to strobe address bits 10-18 into the DRAM on its falling edge, and to perform the refresh in CAS before RAS refresh cycle. DRAM COLUMN ADDRESS STROBE: This output drives the DRAM CAS signal. It is used to strobe address bits 1-9 into the DRAM on its falling edge, and to start a refresh in CAS before RAS refresh cycle. In an early write cycle, it is used to strobe the data into the DRAM. DRAM WRITE: This output is the write signal to the DRAM. It is low during a write cycle, and high at all other times. WAN TRANSMIT DATA: This signal has 2 modes of operation: 1. In synchronous mode, the transmitter emits a new data bit on every falling WTXC edge while WCTS is at a logic low. While WCTS is at a logic high, this pin outputs a logic high. 2. In asynchronous mode, the transmitter emits a start bit, 8 data bits and a stop bit, according to a pre-defined baud rate. WAN TRANSMIT CLOCK / WAN CLOCK: This signal has 2 modes of operation: 1. In synchronous mode, it is the link clock for the transmitter at any frequency up to 40 MHz. 2. In asynchronous mode, it is the clock input to the transmitter and receiver, and is 16 times the baud rate. WAN RECEIVE DATA: This signal has 2 modes of operation: 1. In synchronous mode, it is sampled on every rising edge of WRXC. 2. In asynchronous mode, it is sampled at 16 times the baud rate. WAN RECEIVE CLOCK / BAUD RATE SELECT 0: This signal has 2 modes of operation: 1. In synchronous mode it is the link clock for the receiver at any frequency up to 40 MHz. 2. In asynchronous mode, this signal operates in conjunction with BAUD1 and BAUD2 to determine the baud rate or the clock source. WAN REQUEST TO SEND: This signal is LOW whenever a frame is ready to be transmitted. It goes HIGH when there are no more frames to be transmitted.
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RJ-017
ChipBridge
Table 1. Pin Description (Cont'd) Name
/WCTS
Pin No.
96
Type Description
I WAN CLEAR TO SEND: The transmitter transmits frames while this signal is LOW. In synchronous mode, if this signal goes HIGH for more than one bit-time, the frame in transmission is aborted and retransmitted in its entirety when WCTS goes low again. In asynchronous mode, if this signal goes HIGH, the current byte being transmitted is completed and transmission is suspended until /WCTS goes LOW again. BAUD RATE SELECT 1: In asynchronous mode, this signal operates in conjunction with BAUD0 and BAUD2 to determine the baud rate or the clock source. BAUD RATE SELECT 2: In asynchronous mode, this signal operates in conjunction with BAUD0 and BAUD1 to determine the baud rate or the clock source. COMPRESS ENABLE: When this signal is LOW, frames from the LAN are transmitted over the WAN as is. When this signal is HIGH, the padding bits inserted in sub-64 byte frames are stripped off (Enhanced Tinygram Compression). WAN MODE SELECT: When LOW, the WAN link operates in synchronous mode. When HIGH, the WAN link operates in asynchronous mode. ASYNC CONTROL CHARACTER MAP ENABLE: (valid in asynchronous mode only). When this input pin is LOW, the first 32 characters (up to 0x20) in asynchronous mode are transmitted as a two octet sequence consisting of the Control Escape octet (0x7d) followed by the original octet with its sixth bit complemented. When this pin is HIGH, these characters are transmitted as is. TRANSMIT DATA POSITIVE: This output pin is the positive Manchester encoded data transmitted onto the line. It forms the differential transmit data pair together with TXD-. The transmit data pair can contain both regular transmit data and looped-back receive data, depending on LMODE. DATA PRE-EMPHASIS + / COLLISION OUT+: This output has two purposes. 1. In AUI-DCE modes, it is the positive collision signal. It forms the differential collision pair with TXP-/CO-. The collision signal is a 10 MHz square wave synchronized with CLK10M. 2. In UTP mode, this pin outputs the positive pre-emphasis signal. It forms the differential pre-emphasis pair with TXP-/CO-. TRANSMIT DATA NEGATIVE: This output pin is the negative Manchester encoded data transmitted onto the line. It forms the differential transmit data pair together with TXD+. The transmit data pair can contain both regular transmit data and looped-back receive data, depending on LMODE. DATA PRE-EMPHASIS - / COLLISION OUT -: This output has two purposes. 1. In AUI-DCE mode, it is the negative collision signal. It forms the differential collision pair with TXP+/CO+. The collision signal is a 10 MHz square wave synchronized with CLK10M. 2. In UTP mode, this pin outputs the negative pre-emphasis signal. It forms the differential pre-emphasis pair with TXP+/CO+. RECEIVE DATA INPUT THRESHOLD +: This input pin is used in conjunction with RXDTH- to control the squelch function and link integrity pulse detection. RECEIVE DATA INPUT THRESHOLD -: This input pin is used in conjunction with RXDTH+ to control the squelch function and link integrity pulse detection. RECEIVE DATA INPUT: This input pin receives the serial data from the network and is used by the digital PLL for data recovery. RECEIVE DATA INPUT REFERENCE: This input pin is the reference voltage for the receive input signals RXDTH+, RXDTH- and RXDIN.
BAUD1
98
I
BAUD2 COMPR
95 91
I I
WMODE ACCM
73 92
I I
TXD+
65
O
TXP+/CO+
63
O
TXD-
64
O
TXP-/CO-
62
O
RXDTH+
61
I
RXDTH-
60
I
RXDIN RXDREF
59 58
I I
6
RJ-017
ChipBridge
Table 1. Pin Description (Cont'd) Name
CITH+
Pin No.
57
Type Description
I COLLISION INPUT POSITIVE THRESHOLD: This input pin is used in conjunction with CITH- to detect collisions. It is valid in AUI-DTE mode only. In other modes it should be connected to VDD. COLLISION INPUT NEGATIVE THRESHOLD: This input pin is used in conjunction with CITH+ to detect collisions. It is valid in AUI-DTE mode only. In other modes it should be connected to VDD. COLLISION INPUT REFERENCE: This input pin is the reference voltage for the collision input signals CITH+ and CITH-. It is valid in AUI-DTE mode only. In other modes it should be connected to GND. 10 MHz CLOCK: This is the 10 MHz clock synchronized to the LAN signals RXD, TXD, CRS, CDT, RTS. This clock is used by external logic to sample the outgoing data and control signals, and by the ChipBridge to sample the incoming data and control signals. LAN TRANSMIT DATA: This pin is the transmitted data from the MAC. The data on this pin is synchronized with CLK10M rising edge or falling edge depending on LMODE (see Tables 3 and 4) LAN RECEIVE DATA: This pin is either an input or an output depending on LMODE. 1. When this pin is an input, it is the receive data to the MAC. The data inputted should be synchronous with CLK10M rising edge or falling edge, depending on LMODE. 2. When this pin is an output, it outputs the received data from the ENDEC. This output is synchronized with CLK10M rising edge or falling edge depending on LMODE. (see Tables 3 and 4) LAN CARRIER SENSE: (active LOW or active HIGH, depending on LMODE) This pin is either an input or an output, depending on LMODE. 1. When this pin is an input, it acts as the CRS input to the MAC. The CRS should be synchronous with CLK10M. 2. When this pin is an output, it outputs CRS from the ENDEC. This output is synchronized with CLK10M. (see Tables 3 and 4) LAN COLLISION DETECT: (active LOW or active HIGH, depending on LMODE) This pin is either an input or an output, depending on LMODE. 1. When this pin is an input, it acts as the CDT input to the MAC. The CDT should be synchronous with CLK10M. 2. When this pin is an output, it outputs CDT. This output is synchronized with CLK10M. (see Tables 3 and 4) LAN REQUEST TO SEND: (active LOW or active HIGH, depending on LMODE) This pin is an output, from the MAC. It is asserted whenever the LAN is transmitting. (see Tables 3 and 4) LAN CLEAR TO SEND: (active HIGH) This pin is an input to the LAN DMAs arbiter. When this signal is asserted, the DMAs can transmit data on to the LAN. If this signal is deasserted during transmission, the current frame will be completely transmitted and then transmission will be suspended. FILTER DISABLE: When this input is HIGH, the LAN filter is disabled and all frames are passed transparently. LAN MODE: These input pins select one of the 25 possible LAN operation modes, as described in Table 4.
CITH-
56
I
CIREF
55
I
CLK10M
52
O
LTXD
44
O
LRXD
47
I/O
LCRS
48
I/O
LCDT
50
I/O
LRTS
45
O
LCTS
49
I
FLTDIS LMODE[4:0]
43 66, 67, 68, 69, 70
I I
7
RJ-017
ChipBridge
Table 1. Pin Description (Cont'd) Name
/LNKINT /WANTX /WANRX /LANTX /LANRX /COLL /ERR LP1 LP2 PLLVDD PLLVSS PLLAGND XIN
Pin No.
33 34 35 37 38 39 41 80 79 76 77 78 82
Type Description
OD OD OD OD OD OD OD O I I I O I LINK INTEGRITY: This open drain output pin is LOW, to indicate good link integrity on the TP port during TP mode of operation. WAN TRANSMITTING: This open drain output pin is LOW, to indicate that transmission of data is taking place over the link. WAN RECEIVING: This open drain output pin is LOW, to indicate that data is being received from the link. LAN TRANSMITTING: This open drain output pin is LOW, to indicate that the LAN is transmitting. LAN RECEIVING: This open drain output pin is LOW, to indicate that the LAN is receiving data. COLLISION: This open drain output pin is LOW, to indicate that a collision has occurred on the LAN. ERROR: This open drain output pin is LOW, to indicate that an error has occurred in the bridge, for instance buffer overrun, FIFO overrun/underrun. PHASE DETECTOR OUTPUT: This pin is the output from the phase detector and is connected to an external loop filter. VCO INPUT: This pin is the input to the VCO, and it is connected to an external loop filter. PLL POWER: This pin must be connected to the board's power supply via signal traces that are kept as short as possible. PLL GROUND: This pin must be connected to the board's ground via signal traces as close as possible to the power supply. PLL ANALOG GROUND: This pin must be connected to the board's ground via signal traces as close as possible to the power supply. CRYSTAL INPUT: A 40 MHz crystal must be connected between XIN and XOUT. Alternatively, a clock oscillator may be connected to this pin. This clock is used to drive all the ChipBridge's internal circuitry and CLKOUT output. CRYSTAL OUTPUT: A 40 MHz crystal must be connected between XIN and XOUT. If a clock oscillator was connected to XIN, then this pin should stay unconnected. CLOCK OUTPUT: This is the 20 MHz master clock output. RESET: This active low input is the ChipBridge ASIC reset input. When asserted LOW, all registers are initialized to a known state. POSITIVE SUPPLY VOLTAGE
XOUT
81
O
CLKOUT /RESET VDD
93 84 1, 30, 42, 51, 71, 72, 74, 85, 99 13, 23, 32, 36, 40, 46, 53, 54, 75, 83, 86, 94
O I I
GND
I
GROUND
8
RJ-017
ChipBridge
FUNCTIONAL DESCRIPTION
The ChipBridge performs the bridging function at the MAC (Medium Access Control) level and is transparent to higher level protocols such as TCP/IP, DECnet and IPX, and operating systems such as NetWare and MS LAN manager. It automatically learns all the addresses of the LAN it is connected to. Only broadcasts, multicasts, or frames that are destined for another LAN are forwarded to the WAN. Filtering and forwarding is performed at the maximum theoretical rate of 15,000 pps. Filtering can be disabled if required, by asserting the FLTDIS signal. This feature is useful for extending the physical limits of a network without incurring the penalties associated with using repeaters. The ChipBridge's LAN table can store up to 10,000 addresses. The aging mechanism automatically deletes entries, if no frames have been received from that station for 5 minutes. The ChipBridge buffer can hold 256 frames, with a throughput latency of 1 frame.
In asynchronous mode, HDLC-like framing is used in accordance with RFC 1662. It is an octet-oriented protocol, where each frame starts and ends with the flag sequence (0x7E). Octets are transmitted LSB first, with one start bit, eight bits of data, and one stop bit. All frames contain a 16-bit Cyclic Redundancy Check (CRC) field. Octet stuffing is used for frame transparency in asynchronous mode. Octet stuffing is a procedure where a flag sequence, Control Escape octet (0x7D), or any octet that appears in the AsyncControl-Character-Map (ACCM) is replaced by a two-octet sequence consisting of the Control Escape octet followed by the original octet XORed with 0x20. The ACCM comprises the first 32 characters (up to 0x20). It can be enabled or disabled (characters are transmitted as is) by asserting the ACCM signal. The diagram below shows the structure of the frames transmitted over the WAN. Frame boundaries are defined by flags and all frames are transmitted with a 16-bit CRC. The 32-bit LAN CRC is not transmitted over the WAN.
DA SA TYP DATA E LAN FRAME CRC FLAG
WAN CONTROLLER
The HDLC WAN controller can be configured to operate in synchronous or asynchronous modes. The synchronous HDLC protocol is a bit-oriented protocol, where data is transmitted in frames. Each frame starts and ends with a flag, which is the binary sequence 0111 1110 (0x7E). All frames contain a 16-bit Cyclic Redundancy Check (CRC) field. In synchronous mode, zero-bit insertion is used, to allow the contents of a frame to be transparent. Zero-bit insertion means that a binary 0 is inserted after a succession of five ones within a frame (between flags). 9
FLAG
Enhanced Tinygram Compression increases data throughput. Valid Ethernet frames have a minimum length of 64 bytes. Frames shorter than 64 bytes are padded. With compression enabled (by asserting the COMPR signal), these padding bytes are stripped off before being transmitted over the WAN, and repadded while being received on the other side.
RJ-017
ChipBridge
The example below shows the difference between a typical Ethernet frame before and after compression. Before compression:
DA Bytes: 6 SA 6 Type DATA 2 20 PADDING 26
After compression:
DA Bytes: 6 SA 6 Type DATA 2 20
In asynchronous mode, the three input lines BAUD2, BAUD1 and BAUD0 determine the internal baud rate generator frequency. This frequency can be configured to generate standard frequencies in the range 9.6 kbps to 115.2 kbps, or bypassed when using an external clock, as shown in the table below.
The MAC takes care of all the required functions, such as framing, preamble generation and stripping, addressing, error detection, medium allocation and contention resolution. The ENDEC incorporates the receiver, transmitter, collision, heartbeat, loopback and link integrity blocks, required to implement an IEEE 802.3 compliant AUI or 10BASE-T interface. A smart squelch function is implemented on the receive lines to ensure that noise is not mistaken for a valid signal. The complete physical media interface is achieved with only the addition of passive external components (see Figures 16, 17 and 18 at the end of this data sheet). LAN interface pins are divided into two groups; Manchester encoded pins (used for the AUI and 10BASE-T interfaces) and NRZ pins. There are 25 LAN interface modes selected via the LMODE input lines (see Table 4). In addition to the common modes of operation (such as AUI, UTP half duplex and UTP full duplex), non-standard modes are available for custom applications and glueless connection to most LAN chips. LAN interface modes enable either the Manchester or the NRZ pins, or combinations of the two. Certain NRZ pins can be defined either as inputs or as outputs. LAN interface modes can be grouped into three categories: AUI, UTP and NRZ.
AUI Group
Table 2. Internal Baud Rate Generator Selection BAUD RATE
External Clock 115.2 K 57.6 K 38.4 K 28.8 K 19.2 K 14.4 K 9.6 K
BAUD2 BAUD1 BAUD0
1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0
LAN CONTROLLER
The ChipBridge's CSMA/CD LAN controller fully complies with the IEEE 802.3 Ethernet standard. It integrates a Media Access Controller (MAC) and Manchester Encoder-Decoder (ENDEC) to enable a number of different physical connection schemes.
The AUI group has two categories: AUIDTE and AUI-DCE. The differences between the two categories are summarized below:
AUI-DTE AUI-DCE
Collision Receive Data Loopback SQE Test (heartbeat) Input No Output Yes (if selected)
Not Generated (if applicable selected)
10
RJ-017
ChipBridge
The AUI-DCE mode is used when connecting the ChipBridge directly to a station or a hub, without the need for additional interface circuitry. In this mode, the ChipBridge can draw its power from the AUI interface. In AUI-DCE mode, the ChipBridge behaves like a MAU, in compliance with IEEE 802.3. It generates collisions, and (optionally) loops the received data back. In addition, the SQE test (heartbeat) can be enabled or disabled. SQE test is a self-test feature invoked at the end of each transmission by the DCE. It indicates to the DTE that the collision circuitry is intact and functioning and that the transmission has been recognized. SQE test should be disabled when the ChipBridge is connected to a repeater. The AUI-DTE mode is the Attachment Unit Interface as defined by IEEE 802.3. It is typically used for connecting the ChipBridge to alternative media types, such as coax and fiber optics. External transceivers can be connected to the AUI port to support the 10BASE-2, 10BASE-5 and 10BASE-F standards. In addition to AUI-DTE and AUI-DCE, other modes exist, that combine NRZ and Manchester signals. AUI-DTE-EXT-CDT and AUI-DCE-EXT-CDT allow NRZ control of the collision signal via the CDT input. In AUI-DTE-EXT-RXD and AUI-DCE-EXTRXD modes, the NRZ RXD input is the receive data input and the Manchester receive data is ignored. AUI-DCE-NLB disables the receive data loopback in DCE mode.
UTP Group
UTP-EXT-CDT allows NRZ control of the collision signal via the CDT input. In UTP-EXT-RXD mode, the NRZ RXD input is the receive data input and the Manchester receive data is ignored. In the UTP modes, the polarity of the received signal is automatically corrected if reversed, as in the case of a wiring error.
NRZ Group
The NRZ modes are for interfacing with other Ethernet chips, such as multi-port repeaters or LAN controllers. Signals are at TTL levels. LRXD, LCRS and LCDT are either inputs or outputs, depending on the LAN mode selected (see Table 4). A number of NRZ modes are available for glueless connection to the most common LAN chips available, as summarized in the table 3.
Table 3. NRZ Modes Selection Mode Description LAN NRZ: Controller LMODE Compat- [4..0] ibility
1 TxD, RxD: rising edge RTS, CRS, CDT: active low TxD, RxD: rising edge RTS, CRS, CDT: active high TxD, RxD: falling edge RTS, CRS, CDT: active low TxD, RxD: falling edge RTS, CRS, CDT: active high TxD, RxD: falling edge RTS, CRS: active high CDT: active low 01101
NRZ-FDX: LMODE [4..0]
01111
2
NATIONAL 11100 , AMD, MOTOROLA INTEL, AT&T 11101
11111
3
10111
4
01100
00111
The ChipBridge contains a built-in 10BASE-T transceiver. An IEEE 802.3 compliant 10BASE-T interface is achieved with only the addition of passive external components (see Figure 16). The ChipBridge also supports full-duplex mode (UTP-FDX). 11
5
FUJITSU
11001
RJ-017
ChipBridge
Table 4. LAN Interface Operation Modes
Important Note: The polarity of the NRZ signals for modes not specified in Table 3 is as for mode 1.
LMODE [4..0]
00000 01000
DESCRIPTION
AUI-DTE AUI-DTE-EXTCDT (AUI-DTE with external CDT) AUI-DTE-EXTRXD (AUI-DTE with external RxD) AUI-DCE (regular AUI-DCE) AUI-DCE-NLB (AUI-DCE with no loopback) AUI-DCE-EXTCDT (AUI-DCE with external CDT) AUI-DCE-EXTRXD (AUI-DCE with external RxD) UTP (regular 10BASET) UTP-FDX (Full-duplex UTP) UTP-EXT-CDT (UTP with external CDT) UTP-EXT-CDTRXD (UTP with external CDT and RXD) NRZ (Mode 1) NRZ (Mode 2) NRZ (Mode 3) NRZ (Mode 4)
LTXD
tx data only tx data only
LRXD
output output
NRZ LCDT
output input
LCRS
output output
RXD
receive data receive data
TXD
MANCHESTER TXP/CO
not used not used
tx data only tx data only
00010
tx data only
input
output
input
ignored
tx data only
not used
00011
tx data only
output
output
output
receive data receive data receive data
00100
tx data only
output
output
output
tx and rx data looped back tx data only
00101
tx data only
output
input
output
tx and rx data looped back tx and rx data looped back tx data only
collision generated no SQE collision generated no SQE collision generated no SQE collision generated no SQE preemphasis only preemphasis only preemphasis only preemphasis only not used not used not used not used
00110
tx data only
input
output
input
ignored
00001
tx data only
output
output
output
receive data receive data receive data ignored
10001
tx data only
output
output
output
tx data only
01001
tx data only
output
input
output
tx data only
01011
tx data only
input
input
input
tx data only
01101 11100 11101 01100
tx data only tx data only tx data only tx data only
input input input input
input input input input
input input input input
ignored ignored ignored ignored
tx data only tx data only tx data only tx data only
12
RJ-017
ChipBridge
Table 4. LAN Interface Operation Modes (Cont'd) LMODE [4..0]
11001 01110
DESCRIPTION
NRZ (Mode 5 NRZ-LB (TTL with loopback) NRZ-FDX (Mode 1) NRZ-FDX (Mode 2) NRZ-FDX (Mode 3) NRZ-FDX (Mode 4) AUI-DCE-SQE (regular AUI-DCE with SQE enabled)
LTXD
tx data only tx data only
LRXD
input input
NRZ LCDT
input input
LCRS
input input
RXD
ignored ignored
TXD
MANCHESTER TXP/CO
not used not used
01111 11111 10111 00111 10011
tx data only tx data only tx data only tx data only tx data only
input input input input output
input input input input output
input input input input output
ignored ignored ignored ignored receive data
tx data only tx and rx data looped back tx data only tx data only tx data only tx data only tx and rx data looped back tx data only
not used not used not used not used collision generated SQE generated collision generated SQE generated collision generated SQE generated collision generated SQE generated
10100
10101
10110
AUI-DCE-NLBtx data only SQE (AUI-DCE with no loopback and SQE enabled) AUI-DCE-EXTtx data only CDT-SQE (AUI-DCE with external CDT and SQE enabled) AUI-DCE-EXTtx data only RXD-SQE (AUI-DCE with external RXD and SQE enabled)
output
output
output
receive data
output
input
output
receive data
tx and rx data looped back
input
output
input
ignored
tx and rx data looped back
13
RJ-017
ChipBridge
DRAM
The ChipBridge has a built in DRAM controller to allow glueless connection to a 256k x 16 DRAM. It supports CAS-beforeRAS and RAS-only refresh cycles and all other necessary timing required by the DRAM. DRAM access speed should be 60 ns or faster. Any of the following DRAMS are recommended.
Part Number
1. 2. 3. 4. MT4C16257 M5M44260 MCM54260B MB814260
CLOCK GENERATION
The ChipBridge has a built-in crystal oscillator. The system clock can be generated by external connection of a crystal and RC network, or an external clock source. If an external clock source is used, XIN should be driven and XOUT left floating. If a crystal and RC network is used, see Figure 15 for connection details.
PLL LOOP FILTER
For the PLL to operate properly, an external loop filter is required. See Figure 15 for details of the external loop filter.
Manufacturer
Micron Mitsubishi Motorola Fujitsu
EVALUATION BOARD VISUAL STATUS MONITORING
Seven high drive, open drain, status signals are provided for direct connection of LEDs. These signals provide status indications of link integrity (UTP mode only), WAN and LAN activity, collisions, and system errors. A full featured evaluation board can be ordered separately. The evaluation board contains a complete ChipBridge system, including AUI and UTP LAN media interfaces, LAN NRZ port, an RS-232 WAN interface and status LEDs. The WAN port is also available at TTL levels for connection to physical interfaces other than RS-232.
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
* * * *
Storage Temperature
-65 C to + 150 C
* * *
OPERATING RANGE Operating Temperature
-40 C to +85 C
Ambient Temperature Under Bias
-40 C to +85 C
Supply Voltage
5V +/- 5%
Supply Voltage
-0.3V to + 6.0V
Inputs
VDD + 0.5V < VIN < VSS - 0.5V
Inputs
-0.5V to VDD + 0.5V
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RJ-017
ChipBridge
Table 5. DC Characteristics (Over Operating Range) Symbo Parameter Description l
VIL VIH VT VIL VIH VT VIL VIH VT+ VTVT+ VTVOH
Test Condition
Min
VSS 0.7 VDD
Type Max
0.3 VDD VDD 2.5
Unit
V V V
VOL
IOZ IIN IOS IDD CIN COUT
Voltage Input LOW (CMOS levels) - see note 1 Voltage Input HIGH (CMOS levels) - see note 1 Switching Threshold (CMOS levels) see note 1 Voltage Input LOW (TTL levels) - see note 2 Voltage Input HIGH (TTL levels) - see note 2 Switching Threshold (TTL levels) - see note 2 Voltage Input LOW (PECL levels) - see note 3 Voltage Input HIGH (PECL levels) - see note 3 Schmitt trigger positive going threshold (CMOS levels) - see note 4 Schmitt trigger negative going threshold (CMOS levels) - see note 4 Schmitt trigger positive going threshold (TTL levels) - see note 5 Schmitt trigger negative going threshold (TTL levels) - see note 5 Voltage Output High IOL= -2 mA - see note 6 IOL= -4 mA - see note 7 IOL= -11 mA - see note 8 IOL= -12 mA - see note 9 IOL= -24 mA - see note 10 Voltage Output Low IOL= 2 mA - see note 6 IOL= 4 mA - see note 7 IOL= 11 mA - see note 8 IOL= 12 mA - see note 9 IOL= 24 mA - see note 10 3-state Output Leakage Current VOH = VSS or VDD Input Current VIN = VSS or VDD Output S.C. Current - see note 11 VDD=5.25V, VO=VDD VDD=5.25V, VO=VSS Supply Current VIN = VSS or VDD Input Capacitance Output Capacitance
VSS 2.0 1.5 VSS 4.1 1.77 1.0 1.5 2.0 0.8 2.4 2.4 2.4 2.4 2.4 0.2 0.2 0.2 0.2 0.2 +/- 1 +/- 1 90 -75 1.04
0.8 VDD
V V V
3.3 VDD 2.0
V V V V
2.25
V V V V V V V V V V V V uA uA mA mA mA pF pF
-10 -10 37 -117 2.5 2.0
0.4 0.4 0.4 0.4 0.4 10 10 140 -40 150
NOTES: 1. The following signals have CMOS input levels: ACCM, BAUD1, BAUD2, COMPR, WMODE, LMODE, FLTDIS, MD 2. The following signals have TTL input levels: LRXD, LCRS, LCDT, LCTS. 3. The following signals have PECL input levels: RXDTH+, RXDTH-, RXDIN, CITH+, CITH-. 4. The following signals have CMOS Schmitt trigger inputs: /RESET. 5. The following signals have TTL Schmitt trigger inputs: WTXC, WRXD, WCTS, WRXC.
6. Valid for the following outputs: MA, MD, /MWR, WTXD, WRTS, LTXD, LRTS, LRXD, LCRS, LCDT. 7. Valid for the following outputs: /RAS, /CAS, CLCK10M, CLKOUT. 8. Valid for the following output: XOUT 9. Valid for the following outputs: /LNKINT, /WANTX, /WANRX, /LANTX, /LANRX, /COLL, /ERR. 10. Valid for the following outputs: TXD+, TXD-, TXP+/CO+, TXP-/CO-. 11. Valid for the following outputs: CLCK10M, CLKOUT.
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RJ-017
ChipBridge
Table 6. AC Characteristics (Over Operating Range) Symbo Parameter Description l
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t15 t16 t17 t18 t19 t20 t21 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 Clock low to address valid Clock high to /RAS low Clock low to /RAS high Clock high to /CAS low Clock low to /CAS high Data setup time Data hold time Clock low to /MWR low Clock low to /MWR high Clock low to data valid Clock low to data invalid Clock high to /CAS low (refresh) Clock high to /CAS high (refresh) LCTS setup time Clock high to LRTS asserted Clock high to LTXD valid LCRS setup time LCRS hold time LRXD setup time LRXD hold time LCDT setup time LCDT hold time LCTS hold time Clock high to LRTS disasserted Clock high to LRXD valid Clock high to LCRS asserted/disasserted Clock high to LCDT asserted Clock high to LCDT disasserted TXD+ held high from last valid transition SQE test from TXD inactive CO+ held high from last valid transition SQE test length TXD+ to TXD- skew SQE test signal period
Test Condition
CL = 20 pF CL = 20 pF CL = 20 pF CL = 20 pF CL = 20 pF CL = 20 pF CL = 20 pF CL = 20 pF CL = 20 pF CL = 20 pF CL = 20 pF CL = 20 pF CL = 20 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF
Min
0 0 0 0 4 8 1 0 0 0 0 4 18
Type Max
4 2 2 3 11
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2 2 5 5 3 10
5 8 25 0 8 -2 18 0 0 7 5 5 7 9 350 800 300 700 0.5 100
300
t40 t41
WTXC, WRXC clock period TXC, RXC width high
CL = 50 pF CL = 50 pF
25 10
ns ns
t44 t45 t46
Tx Data delay time WRXD setup time WRXD hold time
CL = 50 pF CL = 50 pF CL = 50 pF
15 0 5
ns ns ns
16
RJ-017
ChipBridge
CLKOUT t1 MA[8..0] (output) ROW t2 /RAS (output) t4 /CAS (output) t8 /MWR (output) t7 t6 MD[15..0] t10 t11 t9 t5 t1 COL t3 ROW COL
Figure 3. Single Cycle DRAM Read and Write Timing
CLKOUT t1 ROW t2 /RAS t4 t5 /CAS t8 /MWR t7 t10 MD[15..0] t11 t6 t9 t1 COL COL COL COL COL t3 ROW COL
MA[8..0]
Figure 4. Burst-Mode DRAM Read and Write Timing
CLKOUT t2 /RAS (output) t12 /CAS (output) t13 t3
Figure 5. DRAM CAS-Before-RAS Refresh Timing
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RJ-017
ChipBridge
t15 CLK10M
t18
t21
t24
t25
t23 LCDT (input) LCTS (input) t16 LRTS (output) t17 LTXD (output) t19 LCRS (input) t20 LRXD (input)
Figure 6. NRZ (Mode 1) Transmit and Receive Timing (inputs)
t15 CLK10M t29 LCDT (output) LCTS (input) t16 LRTS (output) t17 LTXD (output) t28 LCRS (output) t27 LRXD (output) t28 t26 t30
t25
Figure 7. NRZ Transmit and Receive Timing (outputs)
t31 TXD+ t35 TXD-
Figure 8. AUI-DTE Mode Timing
18
RJ-017
ChipBridge
t32 t31 TXD+ t35 TXDt34 t33 CO+ t36 CO-
Figure 9. AUI-DCE Mode Timing
t31 TXD+ TXP+ t35 TXDTXP-
Figure 10. UTP Mode Timing
t40 t41 WTXC /WCTS t44 WTXD t40 t45 t41 WRXC WRXD t46 t44
Figure 11. WAN Synchronous Mode Timing
19
RJ-017
ChipBridge
MECHANICAL SPECIFICATIONS
20
RJ-017
ChipBridge
Physical Dimensions mm
A A1 A2 B D D1 e E E1 L aaa ccc Max Min Min Max Min Max Min Max Min Max BSC Min Max Min Max Min Max Max Max 3.4 0.25 2.55 3.05 0.22 0.38 23.65 24.15 19.90 21.10 0.65 17.65 18.15 13.90 14.10 0.65 1.15 0.10 0.10
in
(0.134) (0.010) (0.100) (0.120) (0.009) (0.015) (0.931) (0.951) (0.783) (0.791) (0.026) (0.695) (0.715) (0.547) (0.555) (0.026) (0.045) (0.004) (0.004)
Notes
1. Coplanarity is the difference between lead and the seating plane, C-. 2. Datums A-B and -D- to be determined at datum plane -H-. 3. To be determined at seating plane -C-. 4. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm/0.010 in. per side. Dimensions D1 and E1 do not include mold mismatch and are determined at datum plane -H-. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. 6. Datum plane -H- is located at the mold parting line and it coincides with the bottom of the leads where the led exits the plastic body.
21
RJ-017
ChipBridge
APPLICATIONS
40MHz
RS-232 LINE DRIVERS
WAN
CHIPBRIDGE
UTP
10BASE-T PHYSICAL INTERFACE (MAGNETICS)
RJ45
DRAM 256kx16
Figure 12. Remote Bridge
40MHz
RJ45
10BASE-T PHYSICAL INTERFACE (MAGNETICS)
UTP
CHIPBRIDGE
WAN
CHIPBRIDGE
UTP
10BASE-T PHYSICAL INTERFACE (MAGNETICS)
RJ45
DRAM 256kx16
DRAM 256kx16
Figure 13. Local Bridge
40MHz
RJ45
RS-232 LINE DRIVERS
WAN
CHIPBRIDGE
NRZ
MULTIPORT REPEATER (HUB)
RJ45
RJ45 DRAM 256kx16
Figure 14. Connection to HUB
22
RJ-017
ChipBridge
CHIPBRIDGE CONNECTION AND INTERFACES
D[0..15] VCC U2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 2 3 4 5 7 8 9 10 31 32 33 34 36 37 38 39 40 35 21 VCC D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 GND GND GND DRAM VCC VCC VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 1 6 20 16 17 18 19 22 23 24 25 26 A0 A1 A2 A3 A4 A5 A6 A7 A8 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A[0..8] 18 19 20 A0 A1 A2 A3 A4 A5 A6 A7 A8 470 21 24 26 28 31 29 27 25 22 84 2 4 6 8 9 11 14 16 17 15 12 10 7 5 3 100 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MWR RAS CAS MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 RESET TXP+/CO+ TXDTXP-/CORXDTHRXDTH+ RXDIN RXDREF CITHCITH+ CIREF LTXD LRXD LCRS LCDT LRTS LCTS LMODE0 LMODE1 LMODE2 LMODE3 LMODE4 WTXD WTXC/WCLK WRXD WRXC/BAUD0 BAUD1 BAUD2 WCTS WRTS COMPR ACCM WMODE FLTDIS CLKOUT CLK10M LNKINT WANTX WANRX LANTX LANRX COLL ERR U3 TXD+ 65 63 64 62 60 61 59 58 56 57 55 44 47 48 50 45 49 66 67 68 69 70 90 89 88 87 98 95 96 97 91 92 73 43 93 52 33 34 35 37 38 39 41 VCC TXD TXC RXD RXC /CTS /RTS RN1 1K TXD+ TXP+/CO+ TXDTXP-/CORXDTHRXDTH+ RXDIN RXDREF CITHCITH+ CIREF
OE WE RAS CASL CASH
27 13 14 29 28
VCC
R18 47K
D7 DIODE R20
VCC
1
S1 C9 C11 30pF
R22 X1 40MHz
100 81 R21 100K 82 VCC 76 80 R19 8K R17 100 77 78 79 XOUT XIN PLLVDD LP1 PLLVSS PLLAGND LP2 CHIPBRIDGE_PQFP
2345678 1 D3 1 2 D8 1 1 D4 1 2 D5 1 1 D2 2 2 D6 2 2 D1 2
C10 22pF
C8 0.01uF
Figure 15. ChipBridge Connection
23
RJ-017
ChipBridge
R29 TXD+ R27 TXP+ R30 TXDR28 TXP-
63.4 C15 390 0.01uF 63.4 390 FGND
U3 1 2 3 16 J1 15 14 1 2 3 4 5 6 7 8 RJ-45 0.01uF FGND VCC R26 8 10BASET MAGNETICS C17 0.01uF C18 0.01uF 9
6 C16 7
11 10
RXDTHC12 R24 390 1.2K
0.01uF RXDIN C13 0.01uF RXDTH+
R25 390 R23 3.3K
C14
R32 50
FGND
0.01uF
R31 50
RXDREF
NOTES: 1. 10BASET MAGNETICS MODULE CONTAINS TRANSFORMER, RX & TX FILTER AND COMMON MODE CHOKE. RECOMMENDED DEVICES: * PULSE: PE-65343 OR PE-68026 * VALOR: SF1012 * BEL: A556-2006-03 * YCL: 20F001N
Figure 16. UTP Interface
24
RJ-017
ChipBridge
R2 TXD+ 100 R1 120 R3 TXD2 4 15 13 100 R4 180 C1 330pF 1 T1 16 +12V P1 8 15 7 14 6 13 RX+ 5 RX- 12 4 11 TX+ 3 TX- 10 CL+ 2 CL- 9 1 CONNECTOR DB15 (FEMALE)
VCC R6 RXDTHC2 R5 220 1K
5 7
12 10
0.01uF RXDIN C3 0.01uF RXDTH+
8 R7 220 R8 3.3K 0.01uF R9 39
9
TRANSFORMER 75uHy
C4
NOTES: 1. RECOMMENDED TRANSFORMERS: R10 39 PULSE: PE-65723 YCL:16PT-004S VALOR: ST-7032
RXDREF
VCC R16 CITHC5 R14 220 1K
0.01uF
0.01uF CITH+
C6
R15 220 R13 3.3K 0.01uF C7
R11 39
R12 39
CIREF
Figure 17. AUI-DTE Interface
25
RJ-017
ChipBridge
R2 TXD+ 100 R1 120 R3 TXD2 4 15 13 100 R4 180 C1 330pF 1 T1 16 P1 8 15 7 14 6 13 TX+ 5 TX- 12 4 11 RX+ 3 RX- 10 CL+ 2 CL- 9 1 CONNECTOR DB15 C4 0.01uF RXDTH+ 3.3K 0.01uF RXDREF R10 39 R7 220 R8 C3 R9 39 NOTES: 1. RECOMMENDED TRANSFORMERS: PULSE: PE-65723 YCL:16PT-004S VALOR: ST-7032
VCC R6 RXDTHC2 R5 220 1K
5 7
12 10
0.01uF RXDIN
8 9 TRANSFORMER 75uHy
R12 TXP+/CO+ 100 R11 120 R13 TXP-/C0100 R14 180 C5 330pF
Figure 18. AUI-DCE Interface
26
RJ-017
ChipBridge
Intentionally left blank
27
ORDERING
The ChipBridge is available in a 100 pin PQFP package. Use the following part numbers when ordering: Description Number ChipBridge 100PQFP Part IC-RJ017
ChipBridge Evaluation Board RJ017EVAL
541-100-06/98
(c) 1998 RAD Data Communications Ltd.
Specifications are subject to change without prior notice.

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